1. Field of the Invention
The present invention relates to the field of logic design for integrated circuits (ICs). More specifically, the present invention relates to a method and an apparatus for removing a pipeline bubble from an execution pipeline.
2. Related Art
Application-Specific Integrated Circuits (ASICs) are quite popular because they facilitate rapid prototyping of new IC chips to satisfy specific customer needs. This rapid prototyping is typically accomplished by interconnecting existing IC building blocks or “standard-cells” within an ASIC to obtain required functionality for specific applications.
As feature sizes continue to shrink and as design tools continue to improve, the complexity of ASICs has grown from ˜5000 gates per chip to over 100 million gates per chip. This allows extremely complex functionality to be integrated into a single ASIC chip.
A common structure within ASIC designs is a pipeline datapath, which comprises a series of consecutive pipeline stages. A stream of data entering from one end of the pipeline propagates through each pipeline stage and eventually emerges from the other end of the pipeline. During this process, each pipeline stage performs a specific operation on the data passing through it.
After each pipeline stage, a pipeline register stores a resulting data value for the next pipeline stage. The pipeline registers are generally coupled to a common clock signal, so that data in the pipeline advances from one pipeline stage to the next in lock-step under control of the clock signal.
A pipeline typically contains a continuous sequence of valid data items. However, if the pipeline encounters an input data stream which contains gaps, for instance a gap due to an idle time between two consecutive values on data inputs, invalid data is inserted in the pipeline. These gaps containing invalid data are commonly referred to as “pipeline bubbles”. Once created, in prior art a pipeline bubble travels along with valid data through the pipeline. Pipeline bubbles are undesirable because they increase data latency and prevent the system from achieving the maximum possible throughput through the pipeline.
Previous techniques to remove pipeline bubbles typically involve adding additional logic between the pipeline stages. One such technique is to insert a data multiplexer (DMUX) before each pipeline register, so that, at each clock cycle, the data within the register may either be advanced to next stage or recirculated back through the DMUX. In doing so, each data item in the pipeline can be independently controlled and manipulated to facilitate removal of a pipeline bubble. However, this technique not only requires changing the pipeline architecture, which can add a significant amount of additional area to the ASIC, but also reduces the maximum possible clock rate, critically compromising performance.
Hence, what is needed is a method and an apparatus for removing pipeline bubbles without significantly affecting the architecture of the pipeline.